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1/13 september 2001 n 5v tolerant inputs and outputs n high speed : t pd = 7.0 ns (max.) at v cc = 3v n power down protection on inputs and outputs n symmetrical output impedance: |i oh | = i ol = 24ma (min) at v cc = 3v n pci bus levels guaranteed at 24 ma n balanced propagation delays: t plh @ t phl n operating voltage range: v cc (opr) = 2.0v to 3.6v (1.5v data retention) n pin and function compatible with 74 series 652 n latch-up performance exceeds 500ma (jesd 17) n esd performance: hbm > 2000v (mil std 883 method 3015); mm > 200v description the 74lcx652 is a low voltage cmos octal bus transceiver and register (3-state) fabricated with sub-micron silicon gate and double-layer metal wiring c 2 mos technology. it is ideal for low power and high speed 3.3v applications; it can be interfaced to 5v signal environment for both inputs and outputs. this device consists of bus transceiver circuits with 3 state, d-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal storage registers. enable (gab) and (gba ) pins are provided to control the transceiver functions. select ab and select ba control pins are provided to select whether real-time or stored data is transferred. a low input level selects real-time, and a high selects stored data. data on the a or b bus, or both, can be stored in the internal d flip-flop by low to high transitions at the appropriate clock pins (cab or cba) regardless of the select or enable control pins. when select ab and select ba are in the real-time transfer mode, it is also possible to store data 74lcx652 low volt. cmos octal bus transceiver/register with 5 volt tolerant inputs and outputs(3-state) pin connection and iec logic symbols order codes package tube t & r sop 74LCX652M1r 74lcx652rm13tr tssop 74lcx652ttr tssop sop
m74lcx652 2/13 without using the internal d-type flip-flops by simultaneously enabling gab or gba . in this configuration each output reinforces its input. it has same speed performance at 3.3v than 5v ac/act family, combined with a lower power consumption. all inputs and outputs are equipped with protection circuits against static discharge, giving them 2kv esd immunity and transient excess voltage. input and output equivalent circuit pin description pin no symbol name and function 1 clock ab (cab) a to b clock input (low to high, edge-triggered) 2 select ab (sab) select a to b source input 3 gab direction control input 4, 5, 6, 7, 8, 9, 10, 11 a1 to a8 a data inputs/outputs 20, 19, 18, 17, 16, 15, 14, 13 b1 to b8 b data inputs/outputs 21 gba output enable input (active low) 22 select ba (sba) select b to a source input 23 clock ba (cba) b to a clock input (low to high, edge triggered) 12 gnd ground (0v) 24 v cc positive supply voltage
m74lcx652 3/13 truth table x : dont care z : high impedance qn : the data stored to the internal flip-flops by most recent low to high transition of the clock inputs * : the data at the a and b bus will be stored to the internal flip-flops on every low to high transition of the clock inputs. gab gba cab cba sab sba a b function lh inputs inputs both the a bus and the b bus are inputs x x x x z z the output functions of the a and b bus are disabled x x inputs inputs both the a and b bus are used for inputs to the internal flip-flops. data at the bus will be stored on low to high transition of the clock inputs. ll outputs inputs the a bus are outputs and the b bus are inputs x* x x l ll the data at the b bus are displayed at the a bus hh x* x l l l the data at the b bus are displayed at the a bus. the data of the b bus are stored to internal flip-flop on low to high transition of the clock pulse hh x*xxh qn x the data stored to the internal flip-flop are displayed at the a bus. x* x h l l the data at the b bus are stored to the internal flip-flop on low to high transition of the clock pulse. the states of the internal flip-flops output directly to the a bus. hh hh inputs outputs the a bus are inputs and the b bus are outputs. xx*l x ll the data at the a bus are displayed at the b bus hh x* l x l l the data at the a bus are displayed at the b bus. the data of the a bus are stored to the internal flip-flop on low to high transition of the clock pulse. hh xx*h x x qn the data stored to the internal flip-flops are displayed at the b bus x* h x l l the data at the a bus are stored to the internal flip-flop on low to high transition of the clock pulse. the states of the internal flip-flops output directly to the b bus. x* h x h h hl outputs outputs both the a bus and the b bus are outputs x x h h qn qn the data stored to the internal flip-flops are displayed at the a and b bus respectively.
m74lcx652 4/13 logic diagram this logic diagram has not be used to estimate propagation delays timing chart
m74lcx652 5/13 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditi ons is not implied 1) i o absolute maximum rating must be observed 2) v o < gnd recommended operating conditions 1) truth table guaranteed: 1.5v to 3.6v 2) v in from 0.8v to 2v at v cc = 3.0v symbol parameter value unit v cc supply voltage -0.5 to +7.0 v v i dc input voltage -0.5 to +7.0 v v o dc output voltage (off state) -0.5 to +7.0 v v o dc output voltage (high or low state) (note 1) -0.5 to v cc + 0.5 v i ik dc input diode current - 50 ma i ok dc output diode current (note 2) - 50 ma i o dc output current 50 ma i cc dc supply current per supply pin 100 ma i gnd dc ground current per supply pin 100 ma t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage (note 1) 2.0 to 3.6 v v i input voltage 0 to 5.5 v v o output voltage (off state) 0 to 5.5 v v o output voltage (high or low state) 0 to v cc v i oh , i ol high or low level output current (v cc = 3.0 to 3.6v) 24 ma i oh , i ol high or low level output current (v cc = 2.7v) 12 ma t op operating temperature -55 to 125 c dt/dv input rise and fall time (note 2) 0 to 10 ns/v
m74lcx652 6/13 dc specifications dynamic switching characteristics 1) number of outputs defined as "n". measured with "n-1" outputs switching from high to low or low to high. the remaining outpu t is measured in the low state. symbol parameter test condition value unit v cc (v) -40 to 85 c -55 to 125 c min. max. min. max. v ih high level input voltage 2.7 to 3.6 2.0 2.0 v v il low level input voltage 0.8 0.8 v v oh high level output voltage 2.7 to 3.6 i o =-100 m av cc -0.2 v cc -0.2 v 2.7 i o =-12 ma 2.2 2.2 3.0 i o =-18 ma 2.4 2.4 i o =-24 ma 2.2 2.2 v ol low level output voltage 2.7 to 3.6 i o =100 m a 0.2 0.2 v 2.7 i o =12 ma 0.4 0.4 3.0 i o =16 ma 0.4 0.4 i o =24 ma 0.55 0.55 i i input leakage current 2.7 to 3.6 v i = 0 to 5.5v 5 5 m a i off power off leakage current 0 v i or v o = 5.5v 10 10 m a i oz high impedance output leakage current 2.7 to 3.6 v i = v ih or v il v o = 0 to v cc 5 5 m a i cc quiescent supply current 2.7 to 3.6 v i = v cc or gnd 10 10 m a v i or v o = 3.6 to 5.5v 10 10 d i cc i cc incr. per input 2.7 to 3.6 v ih = v cc - 0.6v 500 500 m a symbol parameter test condition value unit v cc (v) t a = 25 c min. typ. max. v olp dynamic low level quiet output (note 1) 3.3 c l = 50pf v il = 0v, v ih = 3.3v 0.8 v v olv -0.8
m74lcx652 7/13 ac electrical characteristics 1) skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch- ing in the same direction, either high or low (t oslh = | t plhm - t plhn |, t oshl = | t phlm - t phln |) 2) parameter guaranteed by design capacitive characteristics 1) c pd is defined as the value of the ics internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) = c pd x v cc x f in + i cc /8 (per circuit) symbol parameter test condition value unit v cc (v) c l (pf) r l ( w ) t s = t r (ns) -40 to 85 c -55 to 125 c min. max. min. max. t plh t phl propagation delay time (cab or cba to an or bn) 2.7 50 500 2.5 1.5 9.5 1.5 9.5 ns 3.0 to 3.6 1.5 8.5 1.5 8.5 t plh t phl propagation delay time (an to bn or bn to an) 2.7 50 500 2.5 1.5 8.0 1.5 8.0 ns 3.0 to 3.6 1.5 7.0 1.5 7.0 t plh t phl propagation delay time (sab or sba to an or bn) 2.7 50 500 2.5 1.5 9.5 1.5 9.5 ns 3.0 to 3.6 1.5 8.5 1.5 8.5 t pzl t pzh output enable time (gab, gba to an or bn) 2.7 50 500 2.5 1.5 9.5 1.5 9.5 ns 3.0 to 3.6 1.5 8.5 1.5 8.5 t plz t phz output disable time (gab, gba to an or bn) 2.7 50 500 2.5 1.5 9.5 1.5 9.5 ns 3.0 to 3.6 1.5 8.5 1.5 8.5 t s setup time, high or low level data to cab, cba 2.7 50 500 2.5 2.5 2.5 ns 3.0 to 3.6 2.5 2.5 t h hold time, high or low level data to cab, cba 2.7 50 500 2.5 1.5 1.5 ns 3.0 to 3.6 1.5 1.5 t w cab, cba pulse width, high or low 2.7 50 500 2.5 4.0 4.0 ns 3.0 to 3.6 3.3 3.3 f max clock pulse frequency 3.0 to 3.6 50 500 2.5 150 150 mhz t oslh t oshl output to output skew time (note1, 2) 3.0 to 3.6 50 500 2.5 1.0 1.0 ns symbol parameter test condition value unit v cc (v) t a = 25 c min. typ. max. c in input capacitance 3.3 v in = 0 to v cc 6pf c i/o i/o capacitance 3.3 v in = 0 to v cc 10 pf c pd power dissipation capacitance (note 1) 3.3 f in = 10mhz v in = 0 or v cc 36 pf
m74lcx652 8/13 test circuit c l = 50 pf or equivalent (includes jig and probe capacitance) r l = r1 = 500 w or equivalent r t = z out of pulse generator (typically 50 w ) waveform 1 : propagation delay times (f=1mhz; 50% duty cycle) test switch t plh , t phl open t pzl , t plz 6v t pzh , t phz gnd
m74lcx652 9/13 waveform 2: output enable and disable time (f=1mhz; 50% duty cycle)
m74lcx652 10/13 waveform 3 : setup and hold time, maximum ck frequency (f=1mhz; 50% duty cycle) waveform 4 : pulse width (f=1mhz; 50% duty cycle)
m74lcx652 11/13 dim. mm. inch min. typ max. min. typ. max. a 2.65 0.104 a1 0.1 0.2 0.004 0.008 a2 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 c 0.5 0.020 c1 45 (typ.) d 15.20 15.60 0.598 0.614 e 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 13.97 0.550 f 7.40 7.60 0.291 0.300 l 0.50 1.27 0.020 0.050 s8 (max.) so-24 mechanical data po13t f c l e a1 b1 a e d e3 b 24 13 112 c1 s a2
m74lcx652 12/13 dim. mm. inch min. typ max. min. typ. max. a 1.1 0.043 a1 0.05 0.15 0.002 0.006 a2 0.9 0.035 b 0.19 0.30 0.0075 0.0118 c 0.09 0.20 0.0035 0.0079 d 7.7 7.9 0.303 0.311 e 6.25 6.5 0.246 0.256 e1 4.3 4.5 0.169 0.177 e 0.65 bsc 0.0256 bsc k0 80 8 l 0.50 0.70 0.020 0.028 tssop24 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 7047476a
m74lcx652 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco singapore - spain - sweden - switzerland - united kingdom ? http://www.st.com 13/13

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